1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices and particularly to a nonvolatile semiconductor memory device capable of writing data in a page mode. More specifically, the present invention relates to a structure and a method for reliably writing data in an electrically erasable and programmable ROM (referred to hereinafter as EEPROM) capable of page mode writing.
2. Description of the Background Art
FIG. 8 is a schematic diagram showing an example of an entire structure of a conventional nonvolatile semiconductor memory device.
Referring to FIG. 8, the conventional nonvolatile semiconductor memory device comprises: a memory cell array 1 in which a plurality of memory cells for storing information in a nonvolatile manner are arrayed in a matrix; an X decoder block 2 including an X decoder for selecting one row (a word line) from the memory cell array 1 in response to an X address (a row address) externally applied and a Vpp switch for applying a high voltage Vpp to the selected word line; and a Y decoder 3 for generating a signal for selecting a corresponding column (s) (a corresponding bit line) from the memory cell array 1 in response to a Y address (a column address) externally applied.
In order to write/read data, the above described device comprises: a block 4 including a column latch for temporarily latching data to be written and a Vpp switch for applying the high voltage Vpp to the corresponding bit line at the time of writing the data; a block 5 including a sense amplifier for detecting and amplifying information of a memory cell selected in reading data mode and a write buffer for transmitting external data to be written to the bit line connected to the memory cell selected in writing data mode; a Y gate block 6 connecting the selected bit line(s) to the block 5 in response to a column selection signal from the Y decoder 3; and an I/O buffer 7 for communicating data with the block 5. The I/O buffer 7 receives write data D.sub.IN and supplies it to the write buffer in the block 5. In the meantime, it receives the output of the sense amplifier and provides external read data D.sub.OUT in data reading mode.
As the nonvolatile semiconductor memory device is capable of performing operation in a byte mode, the sense amplifier and the write buffer of the block 5 are arranged for one byte (8 bits) and bit lines for one byte are connected in parallel to the sense amplifiers and the write buffers through the selected Y gates.
Peripheral circuits for controlling the operation in the memory device include: a timer 8 which is enabled in response to a write enable signal WE to define the period of write cycle; a control signal generator 9 which generates various control signals in response to the write enable signal WE and the output of the timer 8; a Vpp generator 10 which generates the high voltage program pulse Vpp and a clock signal .phi. in response to the output of the timer 8; and a V.sub.CGL generator 11 which applies a predetermined potential V.sub.CGL to a control gate line (to be described later) in response to a control signal from the control signal generator 9.
The timer 8 is used to determine an external write cycle and an internal write cycle, which includes an erase cycle and a program cycle.
FIG. 9 is a diagram showing a structure of a main part of the memory device shown in FIG. 8, representing memory cells for one byte and the related portions thereof. The structure shown in FIG. 9 enables input/output of data in a byte unit and a byte selection transistor T3 is provided corresponding to the memory cells for one byte (8 bits).
The memory cells BM for one byte include memory cells MC1 and MC2. Although the memory cells BM for one byte usually comprise eight memory cells, only the two memory cells MC1 and MC2 are typically shown in FIG. 9 for the purpose of simplification.
The memory cell MC1 comprises a memory transistor M1 having a variable threshold voltage Vth, and a select transistor T1 which connects the memory transistor M1 to a bit line BL1 in response to a potential on the corresponding word line WL (the output of the X decoder block 2).
The memory cell MC2 comprises a memory transistor M2, the threshold voltage Vth of which is variable, and a select transistor T2 which connects the memory transistor M2 to a bit line BL2 in response to the potential on the corresponding word line WL.
The byte selection transistor T3 is turned on in response to the potential on the word line WL and transmits a potential on the control gate line CGL to the control gates of the memory transistors M1 and M2.
The sources of the memory transistors M1 and M2 are connected to a ground potential Vss through a transistor T4. The transistor T4 is operative in response to a control signal .phi..sub.SL from the control signal generator (as shown in FIG. 8).
Vpp switches V1, V2 and V3 are provided to apply the high voltage Vpp onto the bit lines BL1 and BL2 and the control gate line CGL. The Vpp switches V1 to V3 include the block 4 shown in FIG. 8.
Column latches C1, C2 and C3 are provided to temporarily latch and hold the potentials (data) on the bit lines BL1, BL2 and the control gate CGL throughout a write cycle. The column latches C1, C2 and C3 each have a JK flip-flop structure.
The column latch C1 comprises: a CMOS inverter including a p channel MOS (insulated gate) transistor Q20 and an n channel MOS transistor Q22; and a CMOS inverter including a p channel MOS transistor Q21 and an n channel MOS transistor Q23. Input and output portions of the respective inverters are cross-connected to constitute a flip-flop type latch.
The column latch C2 comprises: a CMOS inverter including a p channel MOS transistor Q24 and an n channel MOS transistor Q26; and a CMOS inverter including a p channel MOS transistor Q25 and an n channel MOS transistor Q27. Input and output portions of the respective inverters are cross-connected to constitute a flip-flop type latch.
The column latch C3 comprises: a CMOS inverter including a p channel MOS transistor Q28 and an n channel MOS transistor Q30; and a CMOS inverter including a p channel MOS transistor Q29 and an n channel MOS transistor Q31. Input and output portions of the respective inverters are cross-connected to constitute a flip-flop type latch.
One terminal of each of the p channel MOS transistors Q20, Q21, Q24, Q25, Q28 and Q29 is connected to a predetermined power supply potential Vcc. One terminal of each of the n channel MOS transistors Q22, Q23, Q26, Q27, Q30 and Q31 is connected to the ground potential Vss.
Y gate transistors Q15, Q16 and Q17 are provided which connect bit lines selected in response to the output of the Y decoder to the data input/output portions.
The Y gate transistor Q15 is turned on in response to a potential on a Y gate line Y (the output of the Y decoder) and connects the bit line BL1 to the sense amplifier S1 and the driver D1 as the write buffer through an I/O line. A transistor Q18 which is turned on in response to a control signal .phi..sub.W is provided between the I/O line and an output of the driver D1. The Y gate transistor Q16 is turned on in response to the potential on the Y gate line (the output of the Y decoder) to connect the bit line BL2 to the sense amplifier S2 and the driver D2 as the write buffer through the I/O line. A transistor Q19 which is turned on in response to the control signal .phi..sub.W is provided between the I/O line and an output of the driver D2.
A transistor Q17 which is turned on in response to the potential on the Y gate line Y to connect the control gate line CGL and a CGL potential generating circuit CG is provided between the control gate line CGL and the CGL potential generating circuit CG.
FIG. 9 shows the structure in which the sense amplifiers S1 and S2 and the drivers D1 and D2 are provided corresponding to the bit lines BL and BL2, respectively, and the number of bit lines is equal to that of sense amplifiers and drivers. However, in reality, a structure is adopted in which the bit lines BL1 and BL2 are connected to the I/O lines through the transistors Q15 and Q16. The sense amplifiers S1 and S2, and the drivers D1 and D2 are provided only for one byte and the I/O lines are also provided for one byte. Similarly, only one CGL potential generating circuit CG is provided for the control gate line CGL.
Transistors Q6 and Q7 which isolate the bit lines BL1 and BL2 from latch nodes N1 and N2 of the column latches C1 and C2, respectively, in response to a control signal TP are provided between the column latches C1, C2 and the bit lines BL1 and BL2. Similarly, a transistor Q8 which isolates the control gate line CGL from a latch node N3 of the column latch C3 in response to a control signal TE is provided between the control gate line CGL and the column latch C3.
Further, transistors Q9 and Q10 which are turned on in response to a control signal .phi..sub.BR1 to connect the bit lines BL1 and BL2 to the ground potential Vss are provided in association with the bit lines BL1 and BL2.
A transistor Q11 which connects the control gate line CGL to the ground potential Vss in response to a control signal .phi..sub.CR is provided in association with the control gate line CGL.
Transistors Q12 and Q13 which are turned on in response to a control signal .phi..sub.BR2 to connect the latch nodes N1 and N2 to the ground potential Vss are provided to the latch nodes N1 and N2, respectively.
A transistor Q14 which is turned on in response to the control signal .phi..sub.CR to connect the latch node N3 to the ground potential Vss is provided to the latch node N3.
The Vpp switches V1, V2 and V3 which operate responsive to high ("H") level of the potentials on the bit lines BL1 and BL2 and the control gate line CGL to generate the high voltage Vpp are provided for those signal lines, respectively.
FIG. 10 is a view schematically showing a structure of a nonvolatile memory cell, representing an example in which a memory transistor is formed by a floating gate tunnel oxide (FLOTOX) type memory transistor.
A memory transistor is formed in a predetermined region on a P type semiconductor substrate 50 for example and it comprises an N+ type impurity diffused region 51 as a source region, an N+ type impurity diffused region 52 as a drain region, a floating gate 54 for storing charge, and a control gate 55 for controlling operation of the memory transistor. An oxide film 60 of a very thin thickness (about 100 .ANG.) is formed between the floating gate 54 and the N+ type impurity diffused region (drain region) 52, so that electrons are conducted in the form of a tunnel current through the tunnel oxide film 60.
A select transistor comprises an N+ impurity diffused region 52, an N+ type impurity diffused region 53 connected to a bit line BL, and a gate electrode 56 connected to a word line WL.
As described above, the FLOTOX type memory transistor has a gate electrode of a two-layer structure including the control gate 55 (which functions as a normal gate electrode of a MOS transistor) and the floating gate 54 (formed in the electrically floating state between the channel region and the control gate). As a result, the threshold voltage Vth of the memory transistor differs dependent on the quantity of stored electrons in the floating gate 54. Accordingly, if electrons are injected into the floating gate 54, the threshold voltage Vth increases (as shown by .circle.1 in FIG. 11) and if electrons are emitted from the floating gate 54, the threshold voltage Vth decreases (as shown by .circle.2 in FIG. 11).
Thus, since the thin oxide film layer 60 of the thickness of about 100 .ANG. is formed between the drain region 52 and the floating gate 54 of the memory transistor, electrons are injected to and emitted from the above described floating gate 54 when an electric field of about 10 MV/cm is applied to the tunnel oxide film 60 for a period of several ms (miliseconds) to cause tunneling of electrons. The potential between the drain region 52 and the floating gate 54 is mainly dependent on a ratio of the control gate-floating gate capacitance and the floating gate-drain capacitance at the thin oxide film 60. Therefore, in order to attain the above mentioned high electric field of 10 MV/cm, it is necessary to apply the high voltage Vpp of about 15 to 20 V to the control gate 55 or the drain region 52.
FIG. 12 is a diagram showing an example of a construction of a Vpp switch shown in FIG. 9. Referring to FIG. 12, the Vpp switch comprises a transistor Q40 having its one electrode receiving the high voltage Vpp and its gate connected to a bit line BL, a bootstrap capacitance C receiving a clock signal .phi., and a transistor Q41 provided in diode connection between a connection point of the transistor Q40 and the capacitance C and the bit line BL. The high voltage Vpp and the clock signal .phi. are generated from the Vpp generator 10 shown in FIG. 8. Since the transistor Q40 is maintained in the off state in the case of low ("L") level of the potential of the bit line BL as is evident from the above described structure, the high voltage Vpp is not applied to the bit line BL and accordingly the bit line BL is maintained at "L" level. On the other hand, if the potential of the bit line BL is at "H" level, the transistor Q40 is in the on state and accordingly the high voltage Vpp is transmitted to the bit line BL through the transistors Q40 and Q41 by means of the bootstrap capacitance C which raises the voltage for each rise of the clock signal .phi.. Consequently, if the Vpp switch is activated, the potential of the bit line at "H" level is raised to the high voltage Vpp, while if the potential of the bit line BL is at "L" level, the potential is not raised and the bit line BL is maintained at "L" level. A Vpp switch as shown in FIG. 12 is also provided for the control gate CGL.
FIG. 13 is a signal waveform diagram which schematically illustrates data write operation of a nonvolatile semiconductor memory device to which the present invention is applied. As shown in FIG. 13, a data write cycle in the nonvolatile semiconductor memory device includes an external write cycle for receiving externally applied data, and an internal write cycle for actually writing the received write data into the memory cells. The internal write cycle further includes an erase cycle for erasing the memory cell data, and a program cycle for actually writing the received data into the memory cells.
Writing of data is controlled by the write enable signal WE. The external write cycle is so controlled that it is terminated within a predetermined period of time by control signals from an external write cycle timer 1 and an internal write cycle timer 2. More specifically, the timer 1 is started by the activation of the write enable signal WE, namely, the change to "L" level. The timer 1 is reset at each change to "L" level of the write enable signal WE and re-started at each changes to "H" of WE. After completion of the measuring operation of the timer 1 for the predetermined period, the external write cycle is terminated and the internal write cycle is started. Thus, if the write enable signal WE is at "H" level at the end of the measuring operation of the external write timer 1, the external write cycle is terminated and the internal write cycle timer 2 is activated to start the internal write cycle. On the other hand, if the write enable signal WE is at "L" level at the end of the timer 1, the external write cycle is prolonged until the enable signal WE reaches "H" level.
The timer 2 outputs an erase cycle timing signal and a program cycle timing signal in response to an end signal of the timer 1.
The Y gate selection signal is brought to "H" level in a period of "L" level of the write enable signal WE in writing data, whereby valid data is transmitted onto the bit line BL.
FIG. 14 is a signal waveform diagram showing operation of the nonvolatile semiconductor memory device shown in FIG. 9. In the following, the operation of the conventional nonvolatile semiconductor memory device will be described in detail with reference to FIGS. 8 to 14.
Writing cycle of data in the nonvolatile semiconductor memory device (EEPROM) shown in FIG. 9 is divided into an external write cycle (for about 100 .mu.s) for latching externally applied data (of one byte to one page) in the device and an internal write cycle (for 10 ms) applying the high voltage Vpp for changing the threshold voltage Vth of the memory transistors. The internal write cycle is further divided into an erase cycle (a "1" write cycle) for shifting in the positive direction the threshold voltage Vth of all of the selected memory transistors and a program cycle (a "0" write cycle) for shifting in the negative direction the threshold voltages Vth of the memory transistors selected for writing of "0". The time of each cycle is determined by the corresponding timer and after the external write cycle is started, each cycle proceeds automatically under the control of the timer.
First, when the write enable signal WE falls to "L" level, the write cycle is started by activation of the external write cycle timer 1. In response to the fall of the write enable signal WE, the control signals (reset pulses) .phi..sub.BR1, .phi..sub.BR2 and .phi..sub.CR rise to "H" level. As a result, the bit lines BL1 and BL2, the control gate line CGL and the latch nodes N1 to N3 of the column latches reach the ground potential.
Then, the output V.sub.CGL of the CGL potential generating circuit CG rises from the standby potential (the reading potential) to "H" level and the control signals .phi..sub.W, TP and TE also rise to "H" level. Thus, the latch nodes N1 to N3, the bit lines BL1 and BL2 and the control gate line CGL are connected through the transistors Q6 to Q8, respectively. Similarly, the drivers D1 and D2 are connected to the I/O lines through the transistors Q18 and Q19, respectively. In the same manner, in response to the change of the write enable signal WE to "L" level, the potential of the Y gate line Y selected by the Y decoder output rises to "H" level.
Now, description is made of a case in which "0" and "1" are written in the memory cells MC1 and M2, respectively, as an example. In this case, the external write data Din1 and Din2 are brought to "L" and "H" levels, respectively. Accordingly, the outputs of the drivers D1 and D2 are at "H" and "L" levels, respectively. As a result, since the transistors Q6, Q7 and Q15, Q16, Q18 and Q19 are in the on state, the external write data Din1 and Din2 are transmitted to the bit lines BL1 and BL2 through the drivers D1 and D2, respectively, and the potential V.sub.CGL is transmitted onto the control gate line CGL. The potentials transmitted onto the bit lines BL1 and BL2 and the control gate line CGL are latched at the latch nodes N1 to N3 of the column latches C1 to C3, respectively. In this case, "H" level is latched at the latch node N1 and "L" level is latched at the latch node N2. "H" level is latched at the node N3.
Next, when the write enable signal WE rises to "H" level, the control signals .phi..sub.W, TP and TE and the Y decoder output (the potential on the Y gate line) fall to "L" level, whereby the inputting of data of one byte (the byte mode operation) is terminated. In the page mode writing, the above described operation is repeated within a period designated by the timer and inputting of data for one page at the maximum is effected. In this case, if the write enable signal WE is at "H" level at the end of the external write timer 1, the external write cycle is terminated and the internal write cycle is started.
Next, the internal write cycle is executed. In the internal write cycle, all external accesses are inhibited. The change to the internal write cycle is controlled by the timer. First, the control signal .phi..sub.BR1 rises to "H" level and the transistors Q9 and Q10 are turned on, whereby the bit lines BL1 and BL2 are connected to the ground potential. Then, the control signals .phi..sub.SL and TE are both brought to "H" level and the sources of the memory transistors M1 and M2 are connected to the ground potential through the transistor T4. The control gate line CGL is maintained at "H" level. After that, high voltage Vpp pulses for erasure are generated in the Vpp generating circuit. Simultaneously with the generation of the high voltage Vpp pulses, the high voltage Vpp and the clock signal .phi. are applied to the Vpp switches V1 to V3. The bit lines BL1 and BL2 are at "L" level since they are connected to the ground potential, and the Vpp switches V1 and V2 do not operate. Thus, the potentials of the bit lines BL1 and BL2 are maintained at the ground potential. In the meantime, the potential of the control gate line CGL is at "H" level and accordingly it is raised to the high voltage Vpp level by the operation of the Vpp switch V3.
At this time, the potential of the simultaneously selected word line WL is also raised to the high voltage Vpp level by the function of the Vpp switch included in the X decoder block 2. As a result, the drains and sources of the memory transistors M1 and M2 are connected to the ground potential through the transistors T1, T2, the bit lines BL1, BL2 and the transistor T4, while the control gate is raised to the high voltage Vpp level since the potential on the control gate line CGL is transmitted thereto through the transistor T3. As a result, electrons are injected into the floating gates and the threshold voltages Vth of the memory transistors M1 and M2 are both shifted in the positive direction. After that, the high voltage Vpp for erasure falls to "L" level under the control of the timer and the potential of the word line WL and the control signals .phi..sub.SL and TE fall to "L" level, whereby the erase cycle is completed.
Then, the program cycle for writing "0" into the memory cells is started under the control of the timer. In this program cycle, first, the control signal .phi..sub.CR rises to "H" level and the control gate line CGL and the latch node N3 are connected to the ground potential through the transistors Q11 and Q14, respectively.
Subsequently, the control signal TP rises to "H" level and the bit lines BL1 and BL2 are connected to the latch nodes N1 and N2, respectively. Thus, the bit line BL1 is charged up to "H" level by the transference of the potential of the latch node N1 of the column latch C1 which latches "H" level. In the meantime, the bit line BL2 is maintained at the ground potential level since the column latch C2 latches "L" level at the latch node N2. Then, the high voltage Vpp and the clock signal .phi. are generated from the Vpp generator 10 so as to be applied to the Vpp switches V1 to V3 and the Vpp switch of the X decoder block. As a result, the bit line BL1 at "H" level is raised to the high voltage Vpp level and the potential of the selected word line WL is also raised to the high voltage Vpp level. The potential of the bit line BL2 is maintained at "L" level. Consequently, the high voltage Vpp is applied to the drain of the memory transistor M1 through the transistor T1 and the ground potential on the control gate line CGL is transmitted to the control gate of the memory transistor M1 through the transistor T3, with the result that the threshold voltage Vth of the memory transistor M1 is shifted in the negative direction (electrons are emitted from its floating gate). The memory cell M2 is kept in the erase state. Thus, writing of "0" into the memory cell MC1 is completed. Finally, the control signals .phi..sub.BR1 and .phi..sub.BR2 are raised to "H" level and the bit lines BL1 and BL2 are connected to the ground potential. The control signals .phi..sub.CR and TP fall to "L" level and the output potential V.sub.CGL of the CGL potential generating circuit CG is brought to a reading potential (e.g., 0 V of the ground potential level). In consequence, the write cycle is terminated.
In data read operation, a read potential (e.g., 0 V) is applied as the output potential V.sub.CGL from the CGL potential generating circuit CG while the control signals TP, TE, .phi..sub.PR1, .phi..sub.BR2, .phi..sub.CR and .phi..sub.W are maintained at "L" level, and the selected word line WL and Y gate line Y are set to "H" level. More specifically, when the potential of the selected word line WL is raised to "H" level, the transistors T1 to T3 are turned on to cause the memory transistors M1 and M2 to be connected to the bit lines BL1 and BL2, respectively, and to cause the read potential V.sub.CGL to be transmitted to the respective control gates through the transistor T3. As a result, the currents flowing through the bit lines BL1 and BL2 are defined dependent on the information stored in the memory transistors M1 and M2. The impedances of those memory transistors are transmitted to the sense amplifiers S1 and S2 through the transistors Q15 and Q16, respectively, and they are converted to potentials through the sense amplifiers S1 and S2, whereby reading is carried out.
However, in the nonvolatile semiconductor memory device, writing and reading of data are carried out normally for a byte basis or a word basis as described above and writing/reading of data for a one-bit basis cannot be performed independently for the respective memory cells in one byte. More specifically, the source line SL and the control gate line CGL are provided in common for the memory cells of one byte, and, thus, in the erase cycle, the signal .phi..sub.SL rises to "H" level and the source line SL is grounded through the transistor T4. Accordingly, in the erase cycle, since the potential of the selected word line WL and the potential of the control gate line CGL are both at the level of the high voltage Vpp, the select transistors T1 an T2 and the memory transistors M1 and M2 are all to be in the on state and the bit lines BL1 and BL2 are both grounded through the source line SL. Consequently, in a program cycle, when the separation transistors Q6 and Q7 are turned on, the data "0" of the column latch which latches "H" level is inverted and the data cannot be written correctly.
On the other hand, even in an erase cycle, if the source line SL is brought into the electrically floating state by changing the signal to .phi..sub.SL to "L" level to turn off the transistor T4, the bit lines BL1 and BL2 are not grounded through the above described path. However, in this case, the below described difficulties arise because the bit lines BL1 and BL2 are in the electrically floating state and the source line SL is provided in common for the memory cells of one byte. More specifically, if, for example, the potential of the bit line BL1 is "H" level and the potential of the bit line BL2 is "L" level equal to the ground potential level, the bit line BL1 is discharged through a path connecting the selection transistor T1, the memory transistor M1, the source line SL, the memory transistor M2, the selection transistor T2 and the bit line BL2, causing the potential of the bit line BL1 at "H" level to be lowered to "L" level. Also in this case, there is a possibility that the potential of the bit line BL2 at "L" level may be raised to "H" level due to noise caused by charging from the bit line BL1 or coupling capacitance with the Vpp switch, to cause the data latched in the column latch to be inverted in the program cycle. Consequently, in any case, the data latched in the column latch is inverted in the program cycle and the data cannot be written correctly.
In this case (in the case of .phi..sub.SL ="L" level in an erase cycle), the above described difficulties do not occur if a source line for the memory cells of one byte is provided individually for each bit line. However, such a structure requires two connection lines for one pitch of memory cells, which constitutes a considerable difficulty against enhancement of integration scale.
In order to avoid the above described difficulties, it is necessary to increase the latching ability of each column latch and to make each column latch have a capability of charging the bit line from "L" level to "H" level. For those purposes, it is necessary to increase the size of the transistors of each column latch. However, in such a case, the size of the column latch is to be increased and it becomes difficult to provide a column latch in a fine pitch of bit lines, reduced by enhancement of integration scale. Thus, it would be considerably difficult to enhance integration scale of memory devices.
In writing data (in an external data write cycle), it is necessary to invert the level of the latch node of the column latch reset at "L" level to "H" level dependent on input data (write data). Accordingly, the transistors (Q18-Q15-Q6, and Q19-Q16-Q17) which transmit input data to the latch nodes of the column latches, as well as the drivers D1 and D2 need to have abilities (current supply capabilities) for inverting the latch data in the column latches at "L" level to "H" level. This would cause increases in sizes of the respective transistors and drivers, making it difficult to enhance the integration scale of memory devices.
In addition, also with respect to the control gate line, it is necessary for the column latch to have a capability of charging the control gate line at "L" level to "H" level in the external data write cycle. Further, the CGL potential generating circuit and the transistors Q17 and Q8 are required to have capabilities of inverting the latch data in the column latch reset at "L" level to "H" level. In consequence, the sizes of the transistors Q17 and Q8 and the CGL potential generating circuit would be increased similarly, which would a series obstacle to the enhancement of integration scale in semiconductor memory devices.